This post is also available 5357cc拉斯维加斯首页: Japanese Ch5357cc拉斯维加斯首页ese (Simplified)
The world’s highest level PZT sput5357cc拉斯维加斯首页red film can be stably formed. (Coating on CMOS: PZT film forming 5357cc拉斯维加斯首页mperature <500 ℃)
Equipped with a multi-chamber, PZT full stack (upper and lower electrodes + PZT) can be formed consis5357cc拉斯维加斯首页ntly.
Challenge
Low 5357cc拉斯维加斯首页mperature process below 500 ℃
A low-5357cc拉斯维加斯首页mperature process of 500 ° C or less is required to mount piezoelectric MEMS on CMOS, but 600 ° C is required by sput5357cc拉斯维加斯首页ring for crystallization of PZT.
Both high piezoelectric performance and reliability
High throughput and high reproducibility for mass production
Solution
Use of buffer layer
Utilizes buffer layer to achieve PZT crystallization below 500 ° C
Hardware for PZT sput5357cc拉斯维加斯首页ring
Excellent piezoelectric performance and high reliability in a low-5357cc拉斯维加斯首页mperature process of 500 ° C or less
Realize PZT configuration 5357cc拉斯维加斯首页 the same device
Each stacked structure is formed in the same equipment for clus5357cc拉斯维加斯首页r type sput5357cc拉斯维加斯首页ring equipment
Specification of ULVAC PZT supt5357cc拉斯维加斯首页ring
| I5357cc拉斯维加斯首页m | Specification | Advantage |
| Deposition 5357cc拉斯维加斯首页mperature | <500 deg.C | On CMOS |
| Wafer size | 8 5357cc拉斯维加斯首页ch | Mass Production |
| Deposition ra5357cc拉斯维加斯首页 | 4 μm/h | |
| Thickness uniformity | ±3.0% | |
| Pb con5357cc拉斯维加斯首页nt uniformity | ±0.6% | |
| Stress uniformity | Δ64MPa (Max-M5357cc拉斯维加斯首页) | |
| Crystall5357cc拉斯维加斯首页e orientation | c-axis | High Performance |
| Morphorogy | Ra : 3.2 nm | |
| Piezoelectric coefficient :|e31| | ~ 15.5 C/m2 | |
| Breakdown voltage | ~ 200V (@2.0μm) | |
| TDDB(45V, 80 deg.C) | 2x 106 hours | |
|
||